This invention relates to digital logic circuits; and more particularly, it relates to those logic circuits which are capable of being wire-ORed together on a bus.
Basically, any logic circuit receives multiple input signals which have high and low voltage levels that represent a "0" and a "1", and in response it generates output signals as a logical function of the input signals. These output signals also have a high and low voltage levels which represents a "0" and a "1".
Hundreds or even thousands of such circuits are typically integrated and interconnected on a single semiconductor chip. For example, commercially available ECL gate array chips contain over 2,000 logic circuits. These chips generally are soldered into printed circuit boards where they are interconnected via discrete or printed wires to form a digital system.
One type of chip interconnection which works with only certain types of logic circuits is called a wired-OR. With this connection, the output terminals from the logic circuits of several chips are interconnected via a single conductor to a terminating resistor. If the output signal from any one of the logic circuits is at a high voltage level, then the voltage on the terminating resistor is also high; whereas if the output signals from all the logic circuits are at a low voltage level, then the output voltage across the terminating resistor is also low.
This wired-OR type of connection is very useful as a date base. Each of the logic chips which is connected to the bus can send a signal over the bus so long as all of the other logic chips on the bus are generating a low voltage level. However, if some type of fault occurs in any one of the thousands of gates on a chip which causes that chip to erroneously generate a high voltage level on the bus, then the entire bus cannot operate.
Further, it is very difficult to determine which chip on a wire-ORed bus has a fault. For example, if 20 chips are connected to the bus, any one of those 20 chips could be erroneously generating the high voltage level. To determine which chip is faulty, the chips must be physically disconnected from the bus one at a time.
Accordingly, a primary object of the invention is to provide a logic circuit which has three output voltages (rather than just the usual two high and low voltages) to avoid the above described problem.